Mixed Signal Circuit Design

Sebastian Linnhoff, MSc.

 

 

 

Sebastian Linnhoff

Wiss. Mitarbeiter_in

sebastian.linnhoff@tu-berlin.de

+49 30 314-25435

Einrichtung Mixed Signal Circuit Design
Sekretariat EN4
Gebäude E-N
Raum E-N 419

Research Assistant

Research Interests

  • High speed Analog to Digital Converters
  • Time-Interleaved Successive Approximation-Register (SAR) ADCs
  • High resolution pipeline ADCs

Vita

Sebastian Linnhoff received the B.Sc. and M.Sc. of electrical engineering in 2016 and 2018 respectively, both from the Technische Universität Berlin.
During his studies he concentrated on analog circuit design and extended his knowledge during the work on his Bachelor’s Thesis “Analysis of Process Induced Temperature Inversion in 28nm CMOS”. In addition to his master studies he worked as a student assistant at the chair of mixed signal circuit design, where he also completed his Master’s Thesis “Design of a GS/s Pipeline ADC with Parallel-Stage Residue in Deep Submicron CMOS”.
He joined the chair of mixed-signal circuit design in December 2018.

Publikationen

2023

Wittenhagen, E.; Kurth, P.; Hecht, U.; Buballa, F.; Linnhoff, S.; Lotfi, N.; Gerfers, F.
A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS
21th IEEE Interregional NEWCAS Conference (NEWCAS)
Herausgeber: IEEE
2023
Wittenhagen, E.; Artz, P.; Kurth, P.; Linnhoff, S.; Buballa, F.; Scholz, P.; Gerfers, F.
A Bulk-Controlled 12 GS/s Track and Hold Amplifier with >58 dBc SFDR and >53.5 dB SNDR in 22 nm FD-SOI CMOS
18th European Microwave Integrated Circuits Conference (EuMIC)
Herausgeber: IEEE
2023
Kurth, P.; Hecht, U.; Buballa, F.; Linnhoff, S.; Ordouei, H.; Gerfers, F.
A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling
2023 IEEE International Symposium on Circuits and Systems (ISCAS), Seite 1-5
Herausgeber: IEEE
2023

2022

Buballa, F.; Linnhoff, S.; Hoffmann, T.; Wentzel, A.; Heinrich, W.; Gerfers, F.
A 4 GBaud 5 Vpp Pre-Driver for GaN based Digital PAs in 22 nm FDSOI using LDMOS
16th European Microwave Integrated Circuits Conference (EuMIC)
Herausgeber: IEEE
2022

2021

Buballa, F.; Linnhoff, S.; Reinhold, M.; Gerfers, F.
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS
IEEE International Symposium on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2021
Linnhoff, S.; Sippel, E.; Buballa, F.; Reinhold, M.; Vossiek, M.; Gerfers, F.
A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction
IEEE International Symposium on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2021

2020

Linnhoff, S.; Buballa, F.; Reinhold, M.; Gerfers, F.
A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28 nm CMOS
27th International Conference on Electronics, Circuits and Systems (ICECS)
Herausgeber: IEEE
2020

2018

Runge, M.; Linnhoff, S.; Gerfers, F.
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS)
Herausgeber: IEEE
2018