Mixed Signal Circuit Design

Julius Edler, MSc.




Julius Edler

Wiss. Mitarbeiter_in


+49 30 314-22003

Einrichtung Mixed Signal Circuit Design
Sekretariat EN4
Gebäude E-N
Raum E-N 420

Research Assistant

Research Interests

  • Ultra linear Data Converters enabling next generation data communication
  • High-Speed Delta-Sigma Converters
  • High-Linearity OTA Design Techniques

Thesis Offerings

  • Contact me for BA/MA thesis openings
  • Fields: IC Design and characterization of individual building blocks (ADCs, DACs, active filters,  digital logic) using cadence virtuoso and/or System design employing matlab, maple etc.

Julius Edler received the B.Eng. degree from Beuth University and the M.Sc. degree in electrical engineering from TU Berlin. During his studies he gained research experience at Fraunhofer HHI and Leibniz Institute IHP as a student research assistant. Subsequently, he joined the Mixed Signal Circuit Design (MSC) chair in an endeavor to pursue the Ph.D. degree. His research is focused on high-speed high-performance sigma-delta converters. He joined the chair of mixed-signal circuit design in spring 2020.



Wittenhagen, E.; Kurth, P.; Lotfi, N.; Hecht, U.; Edler, J.; Scholz, P.; Gerfers, F.
A 12 GS/s RF-Sampler Employing Inductive Peaking in 22 nm FD-SOI CMOS
18th European Microwave Integrated Circuits Conference (EuMIC)
Herausgeber: IEEE


Runge, M.; Edler, J.; Schmock, D.; Kaiser, T.; Gerfers, F.
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΣΔ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS
Custom Integrated Circuits Conference (CICC)
Herausgeber: IEEE
Artz, P.J.; Edler, J.; Wittenhagen, E.; Lotfi, N.; Gerfers, F.
Workshop WM02 talk: High-Speed ADC (>20 GS/s) with High Resolution (≥10 bit) for Low-IF Receiver in 22nm FDSOI
IEEE European Microwave Week (EuMW) 2021
Edler, J.; Artz, P.J.; Gerfers, F.
Workshop WM02 talk: mm-Wave Advanced-Sampling Transceiver Enabling 6G Data Transmission with 100 Gbit/s per mobile User
IEEE European Microwave Week (EuMW) 2021


Runge, M.; Edler, J.; Kaiser, T.; Gerfers, F.
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS
IEEE Custom Integrated Circuits Conference 2021
Herausgeber: IEEE
Edler, J.; Runge, M.; Gerfers, F.
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seite 1090-1093
Herausgeber: IEEE