Associated Courses:
System-on-Chip - Entwurf und Programmierung (Vorlesung)
System-on-Chip Projekt

Contact Persons
Tobias Kaiser
Marco Liem

Modulzugehörigkeit
System-on-Chip (SOC) + RISC-V Lab

Please register to participate in the  ISIS-Kurs SoC + RISC-V Lab

Where
E 020 (Vorlesung)
MAR 0.011 (Projekt)

When
Monday  12:00 - 14:00  (Vorlesung)
Tuesday 12:00 - 14:00  (Projekt)
Start: 17.04.2023

Learning Outcome

After successful completion of this module, students have gained advanced knowledge about the design of highly complex digital circuits and systems, especially Systems-on-Chip (SoC). Fields of knowledge include: fundamentals of complex SoC design, design flow, IP reuse, hardware-software co-design, SoC architectures, real-time operating systems, processor architectures, memory types and hierarchy, on-chip and off-chip bus systems, test and debug methods.

Furthermore, the students learn following practical skills in the project:
- Use of software tools to design complex digital hardware
- Navigating complex design flows for FPGA and IC development
- Extension of existing digital hardware projects, e. g. by peripheral modules, bus components, interrupt sources, bus masters
- Assessment and evaluation of feasibility and implementation overhead of digital system project ideas
- Successive implementation of digital system project ideas: specification, implementation, verification, demonstration using FPGA prototype

Teaching Content

This module covers advanced concepts and methods of digital hardware design and programming of Systems-on-Chip (SoC) and embedded systems. Contents of the lecture are especially: fundamentals of complex SoC design, design flow, IP reuse, hardware-software co-design, SoC architectures, real-time operating systems, processor architectures, memory types and hierarchy, on-chip and off-chip bus systems, test and debug methods.
 
In the project, groups of 3 - 4 students learn how to practically apply the lecture contents. The students learn to use complex digital design tools with a comprehensive design flow and hardware-software co-design. A FPGA prototype platform is employed. During the introductory phase, a series of exercise sheets is completed. Afterwards, a self-defined project idea is implemented using the example system as a basis.