Mixed Signal Circuit Design

Prof. Dr.-Ing. Friedel Gerfers

 

 

Office EN 4
Building E-N
Room EN 423
Consultation hours by appointment Please contact us via e-mail.

Short Vita

Since 2019: Einstein-Professor of Mixed Signal Circuit Design, Technischen Universität Berlin, Germany
Since 2015: Full Professor, Director of the Chair "Mixed Signal Circuit Design (MSC)", Technische Universität Berlin, Germany
2014 - 2015: Design Manager, High-Speed Data Converters, Apple Inc., USA
2012 - 2014: Director of Engineering, Integrated Device Technology (IDT), San Jose, USA
2005: Dr.-Ing. Degree from the Institute for Microsystems Technology (IMTEK), Albert-Ludwigs-University Freiburg, Germany

Research Topics

The field of application spans from high-speed GS/s integrated circuits (IC) for wireless infrastructure applications (such as LTE base-stations), over energy-efficient DSP-based transceivers for optical applications (such as Silicon Photonics) to ultra-low power readout systems for optical and biomedical sensor as well as the design of ultra-robust automotive integrated circuits. Energy-efficient (RF-) transceiver architectures, energy harvesting approaches for mobile/hand-held devices and the large field of Internet-of-Things (IoT) technologies are additional key research topics.

  •  Data conversion techniques with an emphasis on robustness, energy efficiency as well as silicon area / cost reduction
  •  Low-power wideband wireline- & wireless transceiver, low-noise sensor readout
  •  Mixed-signal error- and mismatch estimation algorithms, (self)-adaptive calibration techniques and highly scalable DSP-based design techniques
  •  Semiconductor design flow, design automation as well as CAD tool development down to 14nm FinFet technologies.

Publications

2022

Artz, P.J.; Gerfers, F.
6G D-Band Receiver Model with High Spectral Efficiency Enabling Global System Optimization
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
Publisher: IEEE
2022
Ordouei, H.; Waldmann, S.; Gerfers, F.
In-Vehicle Network Standards - Overview and Implementation Examples
IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher: IEEE
2022
Kurth, P.; Misselwitz, K.; Scholz, P.; Hecht, U.; Gerfers, F.
A 0.007 mm2 48 - 53 GHz Low-Noise LC-Oscillator using an Ultra-Compact High-Q Resonator
14th German Microwave Conference (GeMiC), Page 104-107
Publisher: IEEE
2022
Edler, J.; Artz, P.J.; Gerfers, F.
Workshop WM02 talk: mm-Wave Advanced-Sampling Transceiver Enabling 6G Data Transmission with 100 Gbit/s per mobile User
IEEE European Microwave Week (EuMW) 2021
2022
Artz, P.J.; Edler, J.; Wittenhagen, E.; Lotfi, N.; Gerfers, F.
Workshop WM02 talk: High-Speed ADC (>20 GS/s) with High Resolution (≥10 bit) for Low-IF Receiver in 22nm FDSOI
IEEE European Microwave Week (EuMW) 2021
2022
Kaiser, T.; Gerfers, F.
Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA
Architecture of Computing Systems (ARCS), Page 33-47
Publisher: Springer International Publishing
2022
Hecht, U.; Wittenhagen, E.; Cirit, H.; Behtash, S.; Venkataram, S.; Gerfers, F.
PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links
IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher: IEEE
2022
Wittenhagen, E.; Kurth, P.; Kaiser, T.; Gerfers, F.
A TI 12 GS/s Sampled Beam-Forming Receiver for a 2x2 Antenna-Array with 69 dBc SFDR
29th International Conference on Electronics, Circuits and Systems (ICECS)
Publisher: IEEE
2022
Artz, P. J.; Scholz, P.; Mausolf, T.; Gerfers, F.
A Fully-Differential 146.6-157.4 GHz LNA Utilizing Back Gate Control to Adjust Gain in 22 nm FDSOI
IEEE MTT-S International Microwave Symposium (IMS)
Publisher: IEEE
2022
Buballa, F.; Linnhoff, S.; Hoffmann, T.; Wentzel, A.; Heinrich, W.; Gerfers, F.
A 4 GBaud 5 Vpp Pre-Driver for GaN based Digital PAs in 22 nm FDSOI using LDMOS
16th European Microwave Integrated Circuits Conference (EuMIC)
Publisher: IEEE
2022
Runge, M.; Edler, J.; Schmock, D.; Kaiser, T.; Gerfers, F.
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΣΔ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS
Custom Integrated Circuits Conference (CICC)
Publisher: IEEE
2022
Wittenhagen, E.; Artz, P.; Scholz, P.; Gerfers, F.
A 3 GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing with >55 dBFS SNR and >67 dBc SFDR up to 3 GHz in 22 nm CMOS SOI
IEEE Open Journal for Circuits and Systems
2022
OpenAccess
Wittenhagen, E.; Hecht, U.; Cirit, H.; Behtash, S.; Venkataram, S.; Gerfers, F.
A 224 Gbit/s Transceiver Front-end Design for Next Generation Data Centers
29th International Conference on Electronics, Circuits and Systems (ICECS)
Publisher: IEEE
2022

2021

Kurth, P.; Hecht, U.; Wittenhagen, E.; Gerfers, F.
A Divider-less Automatic Frequency Calibration for Millimeter-Wave Sub-Sampling Phase-Locked Loops
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Page 718-721
Publisher: IEEE
2021
Gerfers, F.; Runge, M.
Sigma-Delta-Analog-Digital-Converter with gmC-VDAC
2021
Shivapakash, S.; Wiedemann, S.; Becking, D.; Wiedemann, P.; Samek, W.; Gerfers, F.; Wiegand, T.
FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4bit-Compact Multilayer Perceptrons
IEEE Open Journal for Circuits and Systems, 2
2021
Wittenhagen, E.; Runge, M.; Lotfi, N.; Ghafarian, H.; Tian, Y.; Gerfers, F.
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®
IEEE Transactions on Circuits and Systems I: Regular Papers, 68 (1) :57-66
2021
Shivapakash, S.; Jain, H.; Hellwich, O.; Gerfers, F.
A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks
IEEE Open Journal for Circuits and Systems, 2 :161-170
2021
Edler, J.; Runge, M.; Gerfers, F.
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Page 1090-1093
Publisher: IEEE
2021
Linnhoff, S.; Sippel, E.; Buballa, F.; Reinhold, M.; Vossiek, M.; Gerfers, F.
A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction
IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher: IEEE
2021
Ghafarian, H.; Shivapakash, S.; Mortazavi, S.; Scholz, P.; Lotfi, N.; Gerfers, F.
A 9-bit, 45mW, 0.05mm2 Source-Series-Terminated DAC Driver with Echo Canceller in 22nm CMOS for In-Vehicle Communication
IEEE Solid State Circuit Letters, 4 :10-13
2021
Kurth, P.; Misselwitz, K.; Hecht, U.; Gerfers, F.
A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers
IEEE International Symposium on Circuits and Systems (ISCAS), Page 1-5
Publisher: IEEE
2021
Wittenhagen, E.; Artz, P.; Scholz, P.; Gerfers, F.
A 3 GS/s >55 dBFS SNDR Time-Interleaved RF Track and Hold Amplifier with >67 dBc SFDR up to 3 GHz in 22FDX
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Page 139-142
Publisher: IEEE
2021
Runge, M.; Edler, J.; Kaiser, T.; Gerfers, F.
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS
IEEE Custom Integrated Circuits Conference 2021
Publisher: IEEE
2021
Buballa, F.; Linnhoff, S.; Reinhold, M.; Gerfers, F.
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS
IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher: IEEE
2021

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