ExsV SDR Platform
The high performance software designed radio platform designated as ExsV is a versatile system for wireless communication experiments, proof of concept projects, and rapid prototyping. The system has been developed within our research group at TU-Berlin and it consists of compact devices which are equipped with adaptive multi-channel radio frontends, a complex digital system component and standard compatible external data interfaces. The capabilities of the wireless part are not confined to standardized procedures with respect to physical layer (PHY) and medium access control layer (MAC) processing. This makes the system very flexible and suitable for experimental work on new wireless transmission concepts. The devices have been for example successfully utilized as experimental platform for function computations over the wireless channel (see the reference below).
The ExsV devices can be controlled by a central host PC or they can operate independently as stand-alone devices. The central digital unit is based on a complex FPGA for signal processing, system control, and interface control. Complex embedded digital systems and system components can be developed and efficiently implemented by means of high level FPGA design tools such as Intel's DSP Builder. For rapid host PC based project implementation there are all necessary processing elements and interface functions integrated within the standard FPGA project. Host PC interface functions are provided for the Matlab© programming platform, such that device initialization and control as well as signal processing can be implemented in Matlab. No embedded software or programmable hardware customization work is necessary for this kind of hardware in the loop (HIL) system operation.
Beside this HIL function elements the standard FPGA project also contains an OFDM based digital data transceiver which is compatible to a subset of the wireless LAN standard IEEE 802.11. The PHY layer procedures are implemented as programmable hardware architecture and the MAC layer procedures are implemented as embedded microcontroller software. Moreover, there are several function elements integrated within the standard FPGA project for monitoring and testing signals and protocol procedures, such as signal and event recorder.
The four channels of the ExsV radio frontend can be used to implement smart antenna transmission concepts (MIMO, beamforming) or they can be used independently. Main parameters of the radio frontend components can be adapted for different applications in wide ranges. This comprises carrier frequency, sampling frequency, reconstruction filter bandwidth and anti-aliasing filter bandwidth, transmit power, and receiver gain.
Main parameters of the ExsV SDR devices
| Category | Values | Remarks/further specications | |
|---|---|---|---|
| No. of Antennas | 4 | independent RF-chains, SMA connectors | |
| RF carrier frequency range | 700 MHz to 3 GHz | 4 to 6 GHz with optional internal frequency extender | |
| Maximum bandwidth (base band) | 30 MHz | programmable RxADC / TxDAC low pass filter | |
| Sampling frequency | 10 MHz to 40 MHz | single oscillator for all RxADC / TxDAC | |
| RxADC resolution | 12 bit | SQNR: 70 dB | |
| TxDAC resolution | 14 bit | Noise spectral density: <-150 dBc/Hz | |
| Maximum TX power | 15 dBm | per antenna | |
| Receiver noise figure | 6 dB | measured at 2.3 GHz | |
| Internal frequency reference | 20 MHz VCTCXO | stability: 0.28ppm | |
| Optional external frequency reference | 10 MHz to 100 MHz | 50 Ohm, 0 dBm, SMA connector | |
| Power supply | 12VDC, max. 36W | power consumption depends mainly on RF frontend conguration | |
| FPGA resources | equivalent LEs: 256 K total memory: 11.8 Mb embedded multipliers: 736 PLLs: 6 | Intel mid-range FPGA family, model: EP2AGX260 |
Publications
A. Kortke and M. Goldenbaum and S. Stanczak (2014). Analog Computation Over the Wireless Channel: A Proof of Concept. Proc. IEEE Sensors 2014, 1224-1227.