Architektur eingebetteter Systeme

Leitung - Prof. Dr. Ben Juurlink

Biography

Prof. Dr. Ben Juurlink received the M.Sc. degree from Utrecht University, Utrecht, The Netherlands, and the Ph.D. degree from Leiden University, Leiden, The Netherlands, in 1992 and 1997, respectively.

In 1997-1998 he worked as a post-doctoral researcher at the Heinz Nixdorf Institute in Paderborn, Germany, and from 1998 to 2009 he was a faculty member (first assistant professor, then associate professor) of the Computer Engineering Laboratory of Delft University of Technology, Delft, The Netherlands. Currently, he is professor for Embedded Systems Architectures in the Faculty of Electrical Engineering and Computer Science of Berlin University of Technology, Berlin, Germany. He is also co-founder of Spin Digital GmbH.

Dr. Juurlink’s research interests include multi- and many-core processors, reconfigurable computing, and the art of mapping applications effectively and efficiently to computer architectures. He has (co-)authored more than 130 articles in international conferences and journals, and received best paper awards at the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS) in 2002, and at the third IEEE International Conference on Consumer Electronics – Berlin (ICCE-Berlin). He has also received a Technology Transfer Award from the HiPEAC Network of Excellence for transferring some of the video coding technology that has been developed in his group to a Greece-based SME.

Dr. Juurlink is a senior member of the ACM and a senior member of the IEEE. He has been the Principal Investigator of several national research projects, Work Package leader in several European projects, and Coordinator of the EU projects LPGPU, Film265, and LPGPU2. He has served on many program committees, is an editor of the Elsevier journal on Microprocessors and Microsystems: Embedded Hardware Design, and was the general co-chair of the HiPEAC conference in 2013.

Berufserfahrung

Professor for Embedded Systems ArchitecturesBerlin University of Technology, Germany01/2010 - present
Associate professorDelft University of Technology, Netherlands02/2007 - 12/2009
Director of education for master's programs in Computer Engineering and Embedded SystemsDelft University of Technology, Netherlands09/2006 - 12/2009
Assistant professorDelft University of Technology, Netherlands09/1999 - 01/2007
Postdoctoral fellowDelft University of Technology, Netherlands09/1998 - 08/1999
Postdoctoral fellowPaderborn University, Germany01/1997 - 07/1998
Postdoctoral fellowLeiden University, Netherlands09/1996 - 12/1996
Visiting researcherMax-Planck-Institut für Informatik, Saarbrücken, Germany02/1995
Research assistantLeiden University, Netherlands09/1992 - 08/1996
Teaching assistantUtrecht University, Netherlands09/1990 - 01/1992

Ausbildung

PhD degree in computer scienceLeiden University, Netherlands. Thesis title: Computational models for parallel computers02/1997
MSc degree in computer scienceUtrecht University, Netherlands08/1992

Publikationen

2022

Maier, Daniel; Schirmeister, Stefan; Juurlink, Ben
Effects of Approximate Computing on Workload Characteristics
In Schulz, Martin and Trinitis, Carsten and Papadopoulou, Nikela and Pionteck, Thilo, Editor, Architecture of Computing Systems, Seite 85–99
In Schulz, Martin and Trinitis, Carsten and Papadopoulou, Nikela and Pionteck, Thilo, Editor
Herausgeber: Springer International Publishing, Cham
2022
ISBN
978-3-031-21867-5
Fan, Kaijie; Cosenza, Biagio; Juurlink, Ben H. H.
FLEXDP: flexible frequency scaling for energy-delay product optimization of GPU applications
In Luca Sterpone and Andrea Bartolini and Anastasiia Butko, Editor, CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17 - 22, 2022, Seite 177–180
In Luca Sterpone and Andrea Bartolini and Anastasiia Butko, Editor
Herausgeber: ACM
2022
Maier, Daniel; Juurlink, Ben
Model-Based Loop Perforation
Euro-Par 2021: Parallel Processing Workshops, Seite 549–554
Herausgeber: Springer International Publishing, Cham
2022
ISBN
978-3-031-06156-1

2021

Saavedra, Antonio; Nazar, Gabriel L.; Stawinoga, Nicolai; Juurlink, Ben
Evaluation of high-level languages for general FPGA acceleration
Proc. of 17th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES '21)
September 2021
ISBN
978-88-905806-8-0
Maier, Daniel; Cosenza, Biagio; Juurlink, Ben
ALONA: Automatic Loop Nest Approximation with Reconstruction and Space Pruning
In Leonel Sousa and Nuno Roma and Pedro Tomás, Editor, Euro-Par 2021: Parallel Processing, Seite 3–18
In Leonel Sousa and Nuno Roma and Pedro Tomás, Editor
Herausgeber: Springer International Publishing, Cham
2021
ISBN
978-3-030-85665-6

2020

Loni, Mohammad; Zoljodi, Ali; Maier, Daniel; Majd, Amin; Daneshtalab, Masoud; Sjödin, Mikael; Juurlink, Ben; Akbari, Reza
DenseDisp: Resource-Aware Disparity Map Estimation by Compressing Siamese Neural Architecture
IEEE World Congress On Computational Intelligence (WCCI) 2020
Juli 2020
Fan, Kaijie; Cosenza, Biagio; Juurlink, Ben H. H.
Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels
Comput., 8 (2) :37
2020

2019

Drehmel, Robert; Göbel, Matthias; Juurlink, Ben
A Quantitative Analysis of Processor Memory Bandwidth of an FPGA-MPSoC
Proceedings of the 28th Workshop on Parallel Algorithms, Parallel Computer Structures and Parallel System Software (PARS 2019)
2019
Maier, Daniel; Mammeri, Nadjib; Cosenza, Biagio; Juurlink, Ben
Approximating Memory-bound Applications on Mobile GPUs
2019 International Conference on High Performance Computing & Simulation (HPCS)
IEEE
2019
Göbel, Matthias; Clasen, Kai Norman; Drehmel, Robert; Juurlink, Ben
Evaluating the Memory Architecture of Next-Generation FPGA-SoCs for HPC
Proceedings of the 17th International Conference on High Performance Computing & Simulation (HPCS 2019)
Herausgeber: Nominee for Outstanding Paper Award
2019
Hartenstein, Thomas; Maier, Daniel; Cosenza, Biagio; Juurlink, Ben
Memory-aware Weight Pruning for Deep Neural Networks.
PARS-Mitteilungen, (to appear)
2019
Lucas, Jan; Juurlink, Ben
MEMPower: Data-Aware GPU Memory Power Model
In Schoeberl, Martin and Hochberger, Christian and Uhrig, Sascha and Brehm, Jürgen and Pionteck, Thilo, Editor, Architecture of Computing Systems – ARCS 2019, Seite 195–207
In Schoeberl, Martin and Hochberger, Christian and Uhrig, Sascha and Brehm, Jürgen and Pionteck, Thilo, Editor
Herausgeber: Springer International Publishing, Cham
2019
ISBN
978-3-030-18656-2
Fan, Kaijie; Cosenza, Biagio; Juurlink, Ben H. H.
Predictable GPUs Frequency Scaling for Energy and Performance
Proceedings of the 48th International Conference on Parallel Processing, ICPP 2019, Kyoto, Japan, August 05-08, 2019, Seite 52:1–52:10
Herausgeber: ACM
2019
Salehiminapour, Farzaneh; Lucas, Jan; Göbel, Matthias; Juurlink, Ben
Reducing DRAM Accesses through Pseudo-Channel Mode
Proceedings of the 28th Workshop on Parallel Algorithms, Parallel Computer Structures and Parallel System Software (PARS 2019)
Herausgeber: Best Student Paper Award
2019
Lal, Sohan; Lucas, Jan; Juurlink, Ben
SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs
Proc. IEEE Int. Conf on Design Automation, and Test in Europe,(DATE)
2019

2018

Mammeri, Nadjib; Juurlink, Ben
VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs
2018 IEEE International Symposium on Workload Characterization (IISWC)
Herausgeber: IEEE
September 2018
Quast, Christina; Pohl, Angela; Cosenza, Biagio; Juurlink, Ben; Schwemmer, Rainer
Accelerating the RICH Particle Detector Algorithm on Intel Xeon Phi
Parallel, Distributed and Network-based Processing (PDP), 2018 26th Euromicro International Conference on, Seite 368–375
IEEE
2018
Cosenza, Biagio; Popov, Nikita; Juurlink, Ben H. H.; Richmond, Paul; Chimeh, Mozhgan Kabiri; Spagnuolo, Carmine; Cordasco, Gennaro; Scarano, Vittorio
OpenABL: A Domain-Specific Language for Parallel and Distributed Agent-Based Simulations
24th International Conference on Parallel and Distributed Computing (Euro-Par) 2018, Seite 505–518
2018
Göbel, Matthias; Behnke, Ilja; Elhossini, Ahmed; Juurlink, Ben
An Application-Specific Memory Management Unit for FPGA-SoCs
Proceedings of the 25th Reconfigurable Architectures Workshop (RAW 2018) at the 32nd IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018)
Herausgeber: Nominee for Best Short Paper Award
2018
Lal, Sohan; Juurlink, Ben
A Case for Memory Access Granularity Aware Selective Lossy Compression for GPUs
ACM Student Research Competition Poster and Extended Abstract at the 51st IEEE/ACM Int. Symposium on Microarchitecture (MICRO)
2018
Lucas, Jan; Lal, Sohan; Juurlink, Ben
Optimal DC/AC Data Bus Inversion Coding
Proc. Int. Conf on Design Automation, and Test in Europe,(DATE)
2018
Amiri, Hossein; Shahbahrami, Asadollah; Pohl, Angela; Juurlink, Ben
Performance Evaluation of Implicit and Explicit SIMDization
Microprocessors and Microsystems
2018
Herausgeber: Elsevier
Lal, Sohan; Lucas, Jan; Juurlink, Ben
Memory Access Granularity Aware Lossy Compression for GPUs
Proc. 14th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 8)
2018
Pohl, Angela; Cosenza, Biagio; Juurlink, Ben
Control Flow Vectorization for ARM NEON
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, Seite 66–75
2018
Wang, Biao; Souza, Diego Felix; Alvarez-Mesa, Mauricio; Chi, Chi Ching; Juurlink, Ben; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel
Highly Parallel HEVC Decoding for Heterogeneous Systems with CPU and GPU
Signal Processing: Image Communication, 62
2018

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