Architektur eingebetteter Systeme

Publikationen

2018

Wang, Biao; Souza, Diego Felix; Alvarez-Mesa, Mauricio; Chi, Chi Ching; Juurlink, Ben; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel
Highly Parallel HEVC Decoding for Heterogeneous Systems with CPU and GPU
Signal Processing: Image Communication, 62
2018

2017

Habermann, Philipp; Chi, Chi Ching; Alvarez-Mesa, Mauricio; Juurlink, Ben
Application-specific Cache and Prefetching for HEVC CABAC Decoding
:72-85
2017
ISSN: 1070-986X
Wang, Biao; Souza, Diego F.; Alvarez-Mesa, Mauricio; Chi, Chi Ching; Juurlink, Ben; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel
GPU Parallelization of HEVC In-Loop Filters
International Journal of Parallel Programming :1–21
2017
ISSN: 1573-7640
Habermann, Philipp; Chi, Chi Ching; Alvarez-Mesa, Mauricio; Juurlink, Ben
Improved Wavefront Parallel Processing for HEVC Decoding
Proceedings of the 13th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2017), Seite 253-256
2017
ISBN
978-88-905806-5-9
Habermann, Philipp; Chi, Chi Ching; Alvarez-Mesa, Mauricio; Juurlink, Ben
Syntax Element Partitioning for high-throughput HEVC CABAC Decoding
Proceedings of the 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2017), Seite 1308-1312
2017
ISBN
978-1-5090-4116-9
Göbel, Matthias; Elhossini, Ahmed; Chi, Chi Ching; Alvarez-Mesa, Mauricio; Juurlink, Ben
A Quantitative Analysis of the Memory Architecture of FPGA-SoCs
In Wong, Stephan and Beck, Antonio Carlos and Bertels, Koen and Carro, Luigi, Editor
Herausgeber: Best Paper Award winner, Cham
2017
ISBN
978-3-319-56258-2

2016

Wang, Biao; Souza, Diego F.; Alvarez-Mesa, Mauricio; Chi, Chi Ching; Juurlink, Ben; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel
Efficient HEVC decoder for heterogeneous CPU with GPU systems
2016 IEEE 18th International Workshop on Multimedia Signal Processing (MMSP), Seite 1-6
September 2016
Pohl, Angela; Cosenza, Biagio; Mesa, Mauricio Alvarez; Chi, Chi Ching; Juurlink, Ben H. H.
An evaluation of current SIMD programming models for C++
Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector Processing, WPMVP@PPoPP 2016, Barcelona, Spain, March 13, 2016, Seite 3:1–3:8
2016

2015

Chi, Chi Ching; Alvarez-Mesa, Mauricio; Bross, Benjamin; Juurlink, Ben; Schierl, Thomas
SIMD Acceleration for HEVC Decoding
IEEE Transactions on Circuits and Systems for Video Technology, 25 (5) :841-855
Mai 2015
ISSN: 1051-8215
Andersch, Michael; Lucas, Jan; Alvarez-Mesa, Mauricio; Juurlink, Ben
On Latency in GPU Throughput Microarchitectures
Proc. IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS), Seite 169-170
März 2015
Wang, Biao; Alvarez-Mesa, Mauricio; Chi, Chi Ching; Juurlink, Ben
Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL
IEEE Transactions on Circuits and Systems for Video Technology, 25 (3) :525-531
März 2015
ISSN: 1051-8215
Marquez, Gabriel Cebrian; Chi, Chi Ching; Martinez, Jose Luis; Cuenca, Pedro; Mesa, Mauricio Alvarez; Sanz-Rodríguez, Sergio; Juurlink, Ben
Reducing HEVC Encoding Complexity Using Two-Stage Motion Estimation
Visual Communications and Image Processing, VCIP
2015
Sanz-Rodríguez, Sergio; Alvarez-Mesa, Mauricio; Mayer, Tobias; Schierl, Thomas
A Parallel H.264/SVC Encoder for High Definition Video Conferencing
Signal Processing: Image Communication, 30 :89 - 106
2015
ISSN: 0923-5965
Castrillón, Jerónimo; Thiele, Lothar; Schor, Lars; Sheng, Weihua; Juurlink, Ben H. H.; Mesa, Mauricio Alvarez; Pohl, Angela; Jessenberger, Ralph; Reyes, Victor; Leupers, Rainer
Multi/many-core programming: where are we standing?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, Seite 1708–1717
2015
Chi, Chi Ching; Alvarez-Mesa, Mauricio; Juurlink, Ben
Low-Power High-Efficiency Video Decoding Using General-Purpose Processors
ACM Transaction on Architecture and Code Optimization, 11 (4) :56:1–56:25
Januar 2015
Herausgeber: ACM
ISSN: 1544-3566
Göbel, Matthias; Chi, Chi Ching; Alvarez-Mesa, Mauricio; Juurlink, Ben
High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis
Proceedings of the 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2015)
Herausgeber: HiPEAC Paper Award
2015
Lucas, Jan; Andersch, Michael; Alvarez-Mesa, Mauricio; Juurlink, Ben
Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency
ACM Trans. Archit. Code Optim., 12 (3) :32:1–32:26
2015
Herausgeber: ACM
ISSN: 1544-3566

2014

Andersch, Michael; Lucas, Jan; Alvarez-Mesa, Mauricio; Juurlink, Ben
Analyzing GPGPU Pipeline Latency
Proc. 10th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 14)
Juli 2014
Lal, Sohan; Lucas, Jan; Andersch, Michael; Alvarez-Mesa, Mauricio; Elhossini, Ahmed; Juurlink, Ben
GPGPU Workload Characteristics and Performance Analysis
Proc. 14th Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Seite 115-124
Juli 2014
Lucas, Jan; Alvarez-Mesa, Mauricio; Andersch, Michael; Juurlink, Ben
Sparkk: Quality-Scalable Approximate Storage in DRAM
The Memory Forum
Juni 2014

2013

Chi, Chi Ching; Mesa, Mauricio Alvarez; Juurlink, Ben; George, V.; Schierl, T.
Improving the Parallelization Efficiency of HEVC Decoding
Proceedings of the 2012 International Conference on Image Processing (ICIP)
Oktober 2013
Bross, Benjamin; George, Valeri; Alvarez-Mesa, Mauricio; Mayer, Tobias; Chi, Chi Ching; Brandenburg, Jens; Schierl, Thomas; Marpe, Detlev; Juurlink, Ben
HEVC Performance and Complexity for 4K Video
2013 IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin), Seite 44-47
September 2013
Bross, Benjamin; Alvarez-Mesa, Mauricio; George, Valeri; Chi, Chi Ching; Mayer, Tobias; Juurlink, Ben; Schierl, Thomas
HEVC Real-time Decoding
, Proc. SPIE. Applications of Digital Image Processing XXXVIBand8856, Seite 88561R-88561R-11
September 2013
Sanz-Rodríguez, Sergio; Mayer, Tobias; Alvarez-Mesa, Mauricio; Schierl, Thomas
A Low-Complexity Parallel-Friendly Rate Control Algorithm for Ultra-Low Delay High Definition Video Coding
Multimedia and Expo Workshops (ICMEW), 2013 IEEE International Conference on, Seite 1-4
Juli 2013
Lucas, Jan; Lal, Sohan; Alvarez-Mesa, Mauricio; Elhossini, Ahmed; Juurlink, Ben
DART: A GPU Architecture Exploiting Temporal SIMD for Divergent Workloads
Proc. 9th Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy (ACACES' 13)
Juli 2013

Biografie

Mauricio Alvarez Mesa is currently a postdoctoral researcher at the Embedded Systems Architecture group at TU Berlin. He received the MSc degree in Electronic Engineering in 2000 from University of Antioquia, Medellin, Colombia, and the PhD degree in Computer Science in 2011 from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. From 2006 to 2011 he was an adjunct lecturer at UPC. He was a summer intern at IBM Haifa Research labs, Israel in 2007, and a research visitor at Technische Universität Berlin (TU Berlin), Berlin, Germany in 2011. From 2012 to 2013 he was a research associate at the Multimedia Communications group of Fraunhofer Institute HHI in Berlin. At TU Berlin he is currently leading the LPGPU European project and the High Performance Video Coding research line. He has co-authored more than 20 publications in the field of video coding, parallel computing and computer architecture.